The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner. The various layers define circuit components or devices such as transistors.
After the individual devices have been fabricated on the substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally known as “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques. In one interconnection process, called a “dual damascene” technique, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point.
While there exist many variations of a dual-damascene process flow, the process typically begins with deposition of a silicon dioxide dielectric layer of desired thickness which corresponds to the thickness for the via or vias to be etched in the dielectric layer. Next, a thin etch stop layer, typically silicon nitride, is deposited on the dielectric layer. Photolithography is then used to pattern via openings over the etch stop layer, after which dry etching is used to etch via openings in the etch stop layer. The patterned photoresist is then stripped from the etch stop layer after completion of the etch. A remaining dielectric layer the thickness of which corresponds to the thickness of the trench for the metal interconnect lines is then deposited on the etch stop layer, and photolithography followed by dry etching is used to pattern the trenches in the remaining dielectric layer and the vias beneath the trenches. The trench etching stops at the etch stop layer, while the vias are etched in the first dielectric layer through the openings in the etch stop layer and beneath the trenches. Next, a barrier material of Ta or TaN is deposited on the sidewalls and bottoms of the trenches and vias using ionized PVD. A uniform copper seed layer is then deposited on the barrier layer using CVD. After the trenches and vias are filled with copper in a single copper inlay step, the copper overburden extending from the trenches is removed and the upper surfaces of the metal lines planarized using CMP. In the dual damascene process described above, the vias and the trenches are etched in the same step, and the etch stop layer defines the bottom of the trenches. In other variations, the trench is patterned and etched after the via. In the single damascene process, the vias and trenches are individually, rather than simultaneously, filled with copper inlays.
A significant advantage of the dual-damascene process is the creation of a two-leveled metal inlay which includes both via holes and metal line trenches that undergo copper fill at the same time. This eliminates the requirement of forming the trenches for the metal interconnect lines and the holes for the vias in separate processing steps. The process further eliminates the interface between the vias and the metal lines.
Another important advantage of the dual-damascene process is that completion of the process typically requires 20% to 30% fewer steps than the traditional aluminum metal interconnect process. Furthermore, the dual damascene process omits some of the more difficult steps of traditional aluminum metallization, including aluminum etch and many of the tungsten and dielectric CMP steps. Reducing the number of process steps required for semiconductor fabrication significantly improves the yield of the fabrication process, since fewer process steps translate into fewer sources of error that reduce yield.
In both the single damascene and dual damascene techniques, the via sidewalls and via bottom are typically subjected to a reactive clean and physical argon ion bombardment process prior to deposition of the barrier layer onto those surfaces. This is illustrated in FIG. 1A, in which a dual damascene structure 10 is subjected to argon ion bombardment prior to deposition of a barrier layer (not shown) on the structure 10. The dual damascene structure 10 includes a typically copper conductive layer 20, on which is sequentially deposited a via dielectric layer 22 and a trench dielectric layer 24. A via opening 26 and a trench opening 28 are etched in the via dielectric layer 22 and the trench dielectric layer 24, respectively. During the argon ion bombardment cleaning process, argon ions 18 are directed against the trench sidewalls 12, the via sidewalls 14 and the via bottom 16 of the structure 10. However, as shown in FIG. 1B, the argon ion bombardment process has a tendency to cause re-sputtering of metal particles 21 from the conductive layer 20 at the via bottom 16, onto the via sidewalls 14. This disrupts the structural integrity of the damascene profile, adversely affecting device reliability and performance. Accordingly, a method is needed which is suitable for eliminating the requirement for argon ion bombardment cleaning of the via bottom and sidewalls prior to deposition of the barrier layer and seed layer onto those surfaces.
An object of the present invention is to provide a novel method which is suitable for eliminating the need of pre-cleaning a contact opening structure prior to depositing a barrier layer on the structure.
Another object of the present invention is to provide a novel method which is suitable for single damascene, dual damascene and other processes for the fabrication of electrical contacts between conductive layers on a substrate.
Still another object of the present invention is to provide a novel, high kinetic energy method suitable for the deposition of a barrier layer on a contact opening structure.
Yet another object of the present invention is to provide a novel method which is suitable for preventing damage to a copper or other conductive layer beneath a contact opening structure by eliminating the need for pre-clean argon ion bombardment of the conductive layer prior to the formation of a barrier layer in a via, trench or other contact opening opening above the conductive layer.
Another object of the present invention is to provide a novel method which is suitable for preventing sputtering of copper or other metal from a conductive layer beneath a contact opening structure by eliminating the need for pre-clean argon ion bombardment of the conductive layer prior to the formation of a barrier layer in a via, trench or other contact opening opening above the conductive layer.
A still further object of the present invention is to provide a novel method which is capable of improving Rc distribution and reducing the Rc mean value of IC devices on a substrate. In this object of the present invention is to provide a novel method which is capable of improving Rc distribution and reducing the Rc mean value by more re-sputter amount to achieve punch through via bottom (in-situ remove via bottom barrier.
Still another object of the present invention is to provide a novel method which is capable of improving the EM (electro-migration) characteristics of a damascene or other contact opening structure.